ADS5547 Datasheet, PDF (41/50 Pages) Texas Instruments – 14-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5547
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SLWS192 – NOVEMBER 2006
Table 14. CLKOUT Position Programing (continued)
REGISTER ADDRESS
REGISTER DATA
DESCRIPTION
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
<CLKOUT POSN LVDS> – Output clock rising edge programmability in LVDS mode
0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 Default position
0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 Output clock rising edge earlier by (1/12)Ts
0 1100010000 0
0 1 0 1 Output clock rising edge aligned with data
transition
0 1100010000 0
0 1 1 1 Output clock rising edge aligned with data
transition
<CLKOUT POSN LVDS> – Output clock falling edge programmability in LVDS mode
0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 Default position
0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 Output clock falling edge earlier by (1/12)Ts
0 1100010000 1
0 0 0 1 Output clock falling edge aligned with data
transition
0 1100010000 1
1 0 0 1 Output clock falling edge aligned with data
transition
Output Data Format
Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS
(pin 6) or the serial interface register bit <DFS>.
Out-of-range Indicator (OVR)
When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high, and the output code is
clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the output
code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For a negative input
overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format.
Figure 48 shows the behavior of OVR during the overload. Note that OVR and the output code react to the
overload after a latency of 14 clock cycles.
Figure 48. OVR During Input Overvoltage
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