ADS5547 Datasheet, PDF (13/50 Pages) Texas Instruments – 14-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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DESCRIPTION OF PARALLEL PINS
SCLK (Pin 29)
0
DRVDD
Table 3. SCLK Control Pin
DESCRIPTION
LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.
LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.
ADS5547
SLWS192 – NOVEMBER 2006
Table 4. SDATA Control Pin
SDATA (Pin 28)
0
DRVDD
DESCRIPTION
Normal operation (Default)
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
0
(1/3)DRVDD
(2/3)DRVDD
DRVDD
DESCRIPTION
CMOS mode: CLKOUT edge later by (3/12)Ts ⁽¹⁾; LVDS mode: CLKOUT edge aligned with data transition
CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition
CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)Ts
Default CLKOUT position
(1) Ts = 1/Sampling Frequency
DFS (Pin 6)
0
(1/3)DRVDD
(2/3)DRVDD
DRVDD
Table 6. DFS Control Pin
DESCRIPTION
2's complement data and DDR LVDS output (Default)
2's complement data and parallel CMOS output
Offset binary data and parallel CMOS output
Offset binary data and DDR LVDS output
MODE (Pin 23)
0
(1/3)AVDD
(2/3)AVDD
AVDD
Internal reference
External reference
External reference
Internal reference
Table 7. MODE Control Pin
DESCRIPTION
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data.
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