ADS5547 Datasheet, PDF (26/50 Pages) Texas Instruments – 14-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5547
SLWS192 – NOVEMBER 2006
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
SNR vs SAMPLING FREQUENCY
ACROSS POWER SCALING MODES
75
f_IN = 70 MHz
74
73
72
Default
71
70
Power Mode 3
Power Mode 1
69
68
67
66
40
Power Mode 2
60 80 100 120 140 160 180 200 220
F_S − Sampling Frequency − MSPS
Figure 27.
PERFORMANCE vs INPUT AMPLITUDE
105
75.5
95
85
SFDR (dBFS)
75
74.5
75
SNR (dBFS)
65
74
73.5
55
SFDR (dBc)
45
73
72.5
35
25
f_IN = 70 MHz
−60 −50 −40 −30 −20 −10
Input Amplitude − dBFS
72
71.5
0
Figure 29.
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
88
77
f_IN = 10 MHz
86
76
SFDR
84
75
82
80
78
35
SNR
40
45
50
55
60
Input Clock Duty Cycle − %
74
73
72
65
Figure 31.
POWER DISSIPATION vs
SAMPLING FREQUENCY
1.24
1.18 ^{LVDS Mode}
1.12
1.06
Default
1.00
0.94
0.88
0.82
Power Mode 1
0.76
Power Mode 2
0.70
Power Mode 3
0.64
0 20 40 60 80 100 120 140 160 180 200 220
F_S − Sampling Frequency − MSPS
Figure 28.
PERFORMANCE vs CLOCK AMPLITUDE
88
76
86
75
SFDR
84
74
SNR
82
73
80
f_IN = 70 MHz
72
Sine Wave Input Clock
78
71
0.3 0.5 0.8 1.1 1.3 1.5 1.8 2.1 2.3 2.5 2.8
Clock Amplitude - V_PP
Figure 30.
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
40
35
30
25
20
15
10
5
0
Output Code
Figure 32.
26
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