THS1009 Datasheet, PDF (4/31 Pages) Texas Instruments – 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal voltage, fs = 8 MSPS, fI = 2 MSPS at –1 dB (unless otherwise noted)
AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP MAX
SINAD Signal-to-noise ratio + distortion
Differential mode
Single-ended mode
56
59
55
58
SNR Signal-to-noise ratio
Differential mode
Single-ended mode
59
61
58
60
THD Total harmonic distortion
Differential mode
–64
Single-ended mode
–63
ENOB Effective number of bits
Differential mode
Single-ended mode
9 9.5
8.85 9.35
SFDR Spurious free dynamic range
Differential mode
Single-ended mode
61
65
60
64
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, –3 dB
96
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB
54
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, –3 dB
96
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
UNIT
dB
dB
dB
Bits
dB
MHz
MHz
MHz
MHz
TIMING REQUIREMENTS
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal voltage, CL < 30 pF
PARAMETER
tpipe
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Latency
Setup time, CONV_CLK low before CS valid
Setup time, CS invalid to CONV_CLK low
Delay time, CONV_CLK low to SYNC low
Delay time, CONV_CLK low to SYNC high
TEST CONDITIONS
MIN TYP MAX UNIT
5
CONV
CLK
10
ns
20
ns
10 ns
10 ns
4