THS1009 Datasheet, PDF (25/31 Pages) Texas Instruments – 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
Write Timing (using R/W, CS0-controlled)
Figure 32 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1009 can be performed
irrespective of the conversion clock signal CONV_CLK.
tw(CS)
90%
CS0
10%
10%
CS1
R/W^{ÔÔÔÔÔÔÔÔÔ}_10%
RD
tsu(R/W)
D(0–11)
90%
ÓÓÓÓÓÓÓÓÓÓÓÓ ^th(R/W)
10%
tsu
th
90%
Figure 32. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-controlled)
PARAMETER
tsu(R/W)
tsu
th
th(R/W)
tw(CS)
Setup time, R/W stable to last CS valid
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
25