TCM29C13A Datasheet, PDF (4/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TCM29C16A _I/O
TCM29C13A TCM29C14A TCM29C17A
TCM129C13A TCM129C14A TCM129C16A
TCM129C17A
DESCRIPTION
PCM IN
8
10
6
I Receive PCM input. PCM data is clocked in on PCM IN on eight
consecutive negative transitions of the receive data clock, which is
CLKR in fixed-data-rate timing and DCLKR in variable-data-rate
timing.
PCM OUT
13
16
11
O Transmit PCM output. PCM data is clocked out on PCM OUT on eight
consecutive positive transitions of the transmit data clock, which is
CLKX in fixed-data-rate timing and DCLKX in variable-data-rate
timing.
PDN
5
5
4
I Power-down select. The device is inactive with a TTL low-level input
to this PDN and active with a TTL high-level input to this PDN.
PWRO +
2
2
2
O Noninverting output of power amplifier. PWRO + drives transformer
hybrids or high-impedance loads directly in either a differential or a
single-ended configuration.
PWRO –
3
3
3
O Inverting output of power amplifier. PWRO – is functionally identical
with and complementary to PWRO +.
SIGR
8
O Signaling bit output, receive channel. In the fixed-data-rate mode,
SIGR outputs the logical state of the 8th bit (LSB) of the PCM word
in the most recent signaling frame.
SIGX/ASEL
15
18
I A-law and µ-law operation select. When connected to VBB, A-law is
selected. When connected to VCC or GND, µ-law is selected. When
not connected to VBB, it is a TTL-level input that is transmitted as the
eighth bit (LBS) of the PCM word during signaling frames on PCM
OUT (TCM29C14A and TCM129C14A only). SIGX/ASEL is
internally connected to provide µ-law operational for TCM29C16A
and TCM129C16A and A-law operation for TCM29C17A and
TCM129C17A.
TSX/DCLKX
14
17
12
I/O Transmit channel time-slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, TSX/DCLKX is an
open-drain output to be used as an enable signal for a 3-state output
buffer. In the variable-data-rate mode, DCLKX becomes the transmit
data clock, which operates at a TTL level from 64 kHz to 2.048 MHz.
VBB
VCC
1
1
1
20
24
16
Most negative supply voltage. Input is – 5 V ± 5%.
Most positive supply voltage. Input is 5 V ± 5%.
4
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265