TCM29C13A Datasheet, PDF (10/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
Gain relative to gain at 1.02 kHz
TEST CONDITIONS
Below 200 Hz
200 Hz
300 Hz to 3 kHz
Input signal at PCM IN is 0 dBm0 3.3 kHz
3.4 kHz
4 kHz
4.6 kHz
MIN
– 0.5
– 0.15
– 0.35
–1
MAX
0.15
0.15
0.15
0.15
– 0.1
– 14
– 30
UNIT
dB
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 3 and 4)
tc(CLK) Clock period for CLKX, CLKR (2.048-MHz systems)
tr, tf
Rise and fall times for CLKX and CLKR
tw(CLK) Pulse duration for CLKX and CLKR (see Note 7)
tw(DCLK) Pulse duration, DCLK (fDCLK = 64 Hz to 2.048 MHz) (see Note 7)
Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.
MIN
488
5
220
220
45%
NOM
50%
MAX
30
55%
UNIT
ns
ns
ns
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
td(FSX)
tsu(SIGX)
th(SIGX)
Frame-sync delay time
Setup time before bit 7 falling edge of CLKX (TMC29C14A and TCM129C14A only)
Hold time after bit 8 falling edge of CLKX (TCM29C14A and TCM129C14A only)
MIN
MAX
100 tc(CLK) – 100
0
0
UNIT
ns
ns
ns
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
td(FSR)
tsu(PCM _IN)
th(PCM _IN)
Frame-sync delay time
Receive data setup time
Receive data hold time
MIN MAX
100 tc(CLK)–100
50
60
UNIT
ns
ns
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
MIN
MAX
td(TSDX)
td(FSX)
tc(DCLKX)
Time-slot delay time from DCLKX (see Note 8)
Frame sync delay time
Clock period for DCLKX
140 td(DCLKX)–140
100 tc(CLK)–100
488
15620
NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.
UNIT
ns
ns
ns
10
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