DS90LV047ATMX Datasheet, PDF (4/21 Pages) Texas Instruments – DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

DS90LV047A
SNLS044C – MAY 2000 – REVISED APRIL 2013
Switching Characteristics
V_CC = +3.3V ± 10%, T_A = −40°C to +85°C^(1)(2)(3)
Symbol
Parameter
t_PHLD
t_PLHD
t_SKD1
t_SKD2
t_SKD3
t_SKD4
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
f_MAX
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |t_PHLD − t_PLHD|⁽⁴⁾
Channel-to-Channel Skew⁽⁵⁾
Differential Part to Part Skew⁽⁶⁾
Differential Part to Part Skew⁽⁷⁾
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency⁽⁸⁾
Conditions
R_L = 100Ω, C_L = 15 pF
(Figure 3 and Figure 4)
R_L = 100Ω, C_L = 15 pF
(Figure 5 and Figure 6)
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Min
Typ
Max
Units
0.5
0.9
1.7
ns
0.5
1.2
1.7
ns
0
0.3
0.4
ns
0
0.4
0.5
ns
0
1.0
ns
0
1.2
ns
0.5
1.5
ns
0.5
1.5
ns
2
5
ns
2
5
ns
3
7
ns
3
7
ns
200
250
MHz
(1) All typicals are given for: V_CC = +3.3V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r ≤ 1 ns, and t_f ≤ 1 ns.
(3) C_L includes probe and jig capacitance.
(4) t_SKD1 |t_PHLD − t_PLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) t_SKD2 is the Differential Channel-to-Channel Skew of any event on the same device.
(6) t_SKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.
(7) t_SKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min|
differential propagation delay.
(8) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD >
250mV, all channels switching.
Parameter Measurement Information
Figure 2. Driver V_OD and V_OS Test Circuit
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
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