DS90LV047ATMX Datasheet, PDF (13/21 Pages) Texas Instruments – DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

DS90LV047A
www.ti.com
SNLS044C – MAY 2000 – REVISED APRIL 2013
Data Rate vs Cable Length Graph Test Procedure
A pseudo-random bit sequence (PRBS) of 2⁹−1 bits was programmed into a function generator (Tektronix
HFS9009) and connected to the driver inputs via 50Ω cables and SMB connectors. An oscilloscope (Tektronix
11801B) was used to probe the resulting eye pattern, measured differentially at the input to the receiver. A 100Ω
resistor was used to terminate the pair at the far end of the cable. The measurements were taken at the far end
of the cable, at the receiver"s input, and used for the jitter analysis for this graph (Figure 25). The frequency of
the input signal was increased until the measured jitter (t_tcs) equaled 20% with respect to the unit interval (t_tui) for
the particular cable length under test. Twenty percent jitter is a reasonable place to start with many system
designs. The data used was NRZ. Jitter was measured at the 0V differential voltage of the differential eye
pattern. The cables used were LG UTP 4 pair 24 gauge CAT 5 cables. The DS90LV047A and DS90LV048A
were tested using the new LVDS Flow-Evaluation Board LVDS47/48PCB which is available in the
LVDS47/48EVK evaluation kit.
The curve shows very good typical performance that can be used as a design guideline for data rate vs cable
length. Increasing the jitter percentage increases the curve respectively, allowing the device to transmit faster
over longer cable lengths. This relaxes the jitter tolerance of the system allowing more jitter into the system,
which could reduce the reliability and efficiency of the system. Alternatively, decreasing the jitter percentage will
have the opposite effect on the system. The area under the curve is considered the safe operating area based
on the above signal quality criteria. For more information on eye pattern testing, please see TI Application Note
AN-808.
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