CDC925 Datasheet, PDF (4/18 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
spread spectrum clock (SSC) implementation for CDC925
Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency,
which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak.
A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in
Figure 1.
Highest Peak
∆
SSC
Non-SSC
δ of fnom
fnom
Figure 1. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a
“down-spread modulation”.
The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation was driven to keep
the average clock frequency closed to its upper specification limit. The modulation amount was set to
approximately –0.34% (compared to – 0.5% on the CDC924).
In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for
CDC925 is shown in Figure 2.
10.03
10.02
10.01
10
9.99
9.98
9.97
5 10 15 20 25 30 35 40 45
Period of Modulation Signal – µs
Figure 2. SSC Modulation Profile
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