CDC925 Datasheet, PDF (3/18 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
3V66 [0–3]
21, 22, 25, 26
O
3.3 V, Type 5, 66-MHz clock outputs
48MHz
30
O
3.3 V, Type 3, 48-MHz clock output
APIC [0–2]
53, 54, 55
O
2.5 V, Type 1, APIC clock outputs
CPU [0–3]
41, 42, 45, 46
O
2.5 V, Type 1, CPU clock outputs
CPU_DIV2 [0–1]
49, 50
O
2.5 V, Type 1, CPU_DIV2 clock outputs
CPU_STOP
36
I
Disables CPU clock to low state
GND
1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
Ground
PCI [1–7]
9, 11, 12, 14,
O
3.3 V, Type 5, 33-MHz PCI clock outputs
PCI_F
PCI_STOP
PWR_DWN
REF0, REF1
SEL0, SEL1
SEL133/100
SPREAD
VDD3.3V
VDD2.5V
XIN
XOUT
15, 17, 18
8
O
Free-running 3.3-V, Type 5, 33-MHz PCI clock output
37
I
Disables PCI clock to low state
35
I
Power down for complete device with outputs forced low
2, 3
O
3.3 V, Type 3, 14.318-MHz reference clock output
32, 33
I
LVTTL level logic select terminals for function selection
28
I
LVTTL level logic select pins for enabling 100/133 MHz
34
I
Disables SSC function
4, 10, 16, 23,
27, 31, 39
Power for the 3V66, 48MHz, PCI, REF outputs and CORE logic
43, 47, 51, 56
Power for CPU and APIC outputs
5
I
Crystal input – 14.318 MHz
6
O
Crystal output – 14.318 MHz
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