CDC925 Datasheet, PDF (2/18 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
description (continued)
Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an
external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
function tables
INPUTS
SEL133/
100
SEL1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SEL0
L
H
L
H
L
H
L
H
CPU
Hi-Z
N/A
100 MHz
100 MHz
TCLK/2
N/A
133 MHz
133 MHz
CPU_DIV2
Hi-Z
N/A
50 MHz
50 MHz
TCLK/4
N/A
66 MHz
66 MHz
SELECT FUNCTIONS
OUTPUTS
3V66
PCI,
PCI_F
48MHz
Hi-Z
Hi-Z
Hi-Z
N/A
N/A
N/A
66 MHz 33 MHz
Hi-Z
66 MHz 33 MHz 48 MHz
TCLK/4 TCLK/8 TCLK/2
N/A
N/A
N/A
66 MHz
66 MHz
33 MHz
33 MHz
Hi-Z
48 MHz
REF
APIC
FUNCTION
Hi-Z
Hi-Z
3-state
N/A
N/A
Reserved
14.318 MHz 16.67 MHz 48-MHz PLL off
14.318 MHz 16.67 MHz 48-MHz PLL on
TCLK
TCLK/16
Test
N/A
N/A
Reserved
14.318 MHz 16.67 MHz 48-MHz PLL off
14.318 MHz 16.67 MHz 48-MHz PLL on
INPUTS
CPU_STOP PWR_DWN PCI_STOP
X
L
X
L
H
L
L
H
H
H
H
L
H
H
H
CPU
L
L
L
On
On
ENABLE FUNCTIONS
OUTPUTS
CPU_DIV2 APIC 3V66 PCI
L
L
L
L
On
On
L
L
On
On
L
On
On
On
On
L
On
On
On
On
PCI_F
L
On
On
On
On
REF,
48MHz
L
On
On
On
On
INTERNAL
Crystal VCOs
Off
Off
On
On
On
On
On
On
On
On
BUFFER NAME
CPU, CPU_DIV2, APIC
48MHz, REF
PCI, PCI_F, 3V66
OUTPUT BUFFER SPECIFICATIONS
VDD RANGE
(V)
IMPEDANCE
(Ω)
2.375 – 2.625
13.5 – 45
3.135 – 3.465
20 – 60
3.135 – 3.465
12 – 55
BUFFER TYPE
TYPE 1
TYPE 3
TYPE 5
2
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