CDC5801A Datasheet, PDF (4/18 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT

CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
PLL divider/multiplier selection
Table 1 and Table 2 list the supported REFCLK and BUSCLK (CLKOUT/CLKOUTB) frequencies.
Table 1. Multiplication Ratios (P0:2 = 000 or 100)
MULT0
0
0
1
MULT1
0
1
1
REFCLK
(MHZ)
38−125
25−83.3
19−62.5
MULTIPLICATION
RATIO
4
6
8
BUSCLK
(MHZ)
152−500
150−500
152−500
Table 2. Divider Ratio (P0:2 = 001)
MULT0
MULT1
REFCLK
(MHZ)
DIVISION
RATIO
BUSCLK(1)
(MHZ)
0
0
100−125
2
50−62.5
1
0
75−93
3
25−31
1
1
50−62
4
12.5−15.5
† _{BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying}
REFCLK, the PLL requires stabilization time to achieve phase lock.
STATE
Powerdown
CLK stop
Normal
Table 3. Clock Output Driver States
PWRDNB
0
1
1
STOPB
X
0
1
CLKOUT
GND
VO, _STOP
As per Function Table
CLKOUTB
GND
VO, _STOP
As per Function Table
Table 4. Programmable Delay and Phase Alignment
DLYCTRL
LEADLAG
CLKOUT AND CLKOUTB
Each rising edge†
1
Will be advanced by one step size (see Table 5)
Each rising edge†
0
Will be delayed by one step size (see Table 5)
† _{For every 32nd edge, there are one or two edges the phase aligner does not update. Therefore,}
CLKOUT phase is not updated on every 32nd edge.
Table 5. Clock Output Driver States
FUNCTIONALITY
STEP SIZE
Multiply by 4, 6, 8
CLKOUT period/384 (for example, 6.5 ps at 400 MHz)
Divide by 2
CLKOUT period/3072 (for example, 6.5 ps at 50 MHz)
Divide by 3
CLKOUT period/6144 (for example, 6.5 ps at 25 MHz)
Divide by 4
CLKOUT period/12288 (for example, 6.5 ps at 12.5 MHz)
NOTE: The frequency of the DLYCTRL terminal must always be equal or less than the
frequency of the LEADLAG terminal.
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