CDC5801A Datasheet, PDF (2/18 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT

CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with
the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality.
Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output
the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a
high impedance state. This device has another unique capability to be able to function with a wide band of
voltages on the REFCLK terminal by varying the voltage on the V_DDREF terminal.
The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.
The CDC5801A device is characterized for operation over free-air temperatures of −40°C to 85°C.
functional block diagram
PWRDWNB P0
P1
P2
STOPB
Control Logic
REFCLK
B
VDDREF/2
PLLCLK
Phase Aligner
Bypass MUX
PLL
Phase
Aligner
Divider
Ratio
φ_D
A
CLKOUT
CLKOUTB
2 MULT0/DIV0
MULT1/DIV1
VDDPD/2
DLYCTRL LEADLAG
2
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