CDC5801A Datasheet, PDF (3/18 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT

CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
FUNCTION TABLE†
MODE
P0 P1 P2
CLKOUT/CLKOUTB
Multiplication with programmable 0 0 0 REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs
delay and phase alignment active‡
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Division with programmable delay 0 0 1 REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs
and phase alignment active ^‡
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Multiplication only mode (phase
aligner bypassed) ^§
1 0 0 In this mode one can only multiply as per Table 1. Programmable delay capability
and divider capability is deactivated. PLL is running.
Test mode
1 1 0 PLL and phase aligner both bypassed. REFCLK is directly channeled to output.
Hi-Z mode
0 1 X Hi-Z
† _{X = don’t care, Hi-Z = high impedance}
‡ _{Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions.}
§ _{In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay}
of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.
Terminal Functions
TERMINAL
NAME
NO.
CLKOUT
20
CLKOUTB
18
DLYCTRL
7
GND
GNDO
GNDP
GNDPA
LEADLAG
MULT0/DIV0
MULT1/DIV1
NC
PWRDNB
P0
P1
P2
REFCLK
STOPB
VDDPA
VDDPD
VDDREF
VDDO
VDDP
5
17, 21
4
8
6
15
14
19
12
24
23
13
2
11
9
10
1
16, 22
3
I/O
DESCRIPTION
O Output clock
O Output clock (complement)
I Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the
CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising
edges). See Table 4.
GND for VDDREF and VDDPD
GND for clock output terminals (CLKOUT, CLKOUTB)
GND for PLL
GND for phase aligner
I Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4.
I PLL multiplier and divider select
I PLL multiplier and divider select
Not used
I Active low power down state, CLKOUT/CLKOUTB goes low
I Mode control, see the Function Table
I Mode control, see the Function Table
I Mode control, see the Function Table
I Reference input clock
I Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3
I Supply voltage for phase aligner
I Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function
I Reference voltage for REFCLK
I Supply voltage for the output terminals (CLKOUT, CLKOUTB)
I Supply voltage for PLL
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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