BQ24250C_15 Datasheet, PDF (4/46 Pages) Texas Instruments – bq24250C 2A Single Input I2C, Standalone Switch-Mode Li-Ion Battery Charger with Power-Path Management

bq24250C
SLUSBY7 – JULY 2014
6 Pin Configuration and Functions
YFF Package
(30-Ball 2.4 mm × 2 mm DSBGA)
Top View
1
2
3
4
5
A
BAT
SYS
PGND
SW
IN
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B
BAT
SYS
PGND
SW
IN
C
BAT
SYS
PGND
SW
IN
D
ISET
EN2
EN1
/CE
PMID
E
INT
SCL
STAT
VDPM BOOT
PIN
NAME
AGND
BAT
BOOT
CE
CHG
EN1
EN2
ILIM
IN
INT
bq24250C
YFF
–
A1, B1, C1
E5
D4
–
D3
D2
F5
A5,B5,C5
E1
F
TS
SDA
PGND
LDO
ILIM
bq24250C
RGE
4
11–12
21
1
–
2
3
22
19
8
bq24250C
Pin Descriptions
I/O
DESCRIPTION
Analog Ground for QFN only. Connect to the thermal pad and the ground plane
of the circuit.
I/O
Battery Connection. Connect to the positive pin of the battery. Additionally,
bypass BAT with a >1μF capacitor.
High Side MOSFET Gate Driver Supply. Connect a 0.033μF ceramic capacitor
I (voltage rating > 15V) from BOOT to SW to supply the gate drive for the high
side MOSFETs.
I
Charge Enable Active-Low Input. Connect CE to a high logic level to place the
battery charger in standby mode.
Charge Status Open Drain Output. CHG is pulled low when a charge cycle
O
starts and remains low while charging. CHG is high impedance when the
charging terminates and when no supply exists. CHG does not indicate
recharge cycles.
I Input Current Limit Configuration Inputs. Use EN1, and EN2 to control the
maximum input current and enable USB compliance. See Table 1 for
I _{programming details.}
Input Current Limit Programming Input. Connect a resistor from ILIM to GND to
I
program the input current limit for IN. The current limit is programmable from
0.5A to 2A. ILIM has no effect on the USB input. If an external resistor is not
desired, short to GND for a 2A default setting.
I
Input power supply. IN is connected to the external DC supply (AC adapter or
USB port). Bypass IN to PGND with >2μF ceramic capacitor
Status Output. INT is an open-drain output that signals charging status and
fault interrupts. INT pulls low during charging. INT is high impedance when
O
charging is complete or the charger is disabled. When a fault occurs, a 256μs
pulse is sent out as an interrupt for the host. INT will indicate recharge cycles.
Connect INT to a logic rail through a 10kΩ resistor to communicate with the
host processor.
4
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