BQ24250C_15 Datasheet, PDF (27/46 Pages) Texas Instruments – bq24250C 2A Single Input I2C, Standalone Switch-Mode Li-Ion Battery Charger with Power-Path Management

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bq24250C
SLUSBY7 – JULY 2014
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
START
Condition
1
2
8
Figure 25. Acknowledge on the I2C Bus
9
Clock Pulse for
Acknowledgement
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPEATED START
Condition
P
Sr
SCL
S
or
Sr
R/W
ACK
Sr
ACK
or
P
Figure 26. Bus Protocol
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