BQ24250C_15 Datasheet, PDF (26/46 Pages) Texas Instruments – bq24250C 2A Single Input I2C, Standalone Switch-Mode Li-Ion Battery Charger with Power-Path Management

bq24250C
SLUSBY7 – JULY 2014
www.ti.com
8.4.14 Serial Interface Description
The bq24250C uses an I²C compatible interface to program charge parameters. I²C is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I²C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device.
Thebq24250C device works as a slave and supports the following data transfer modes, as defined in the I²C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I²C circuitry is powered from IN when a supply is connected.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24250C device only supports 7-bit addressing. The device 7-bit address is
defined as ‘1101010’ (0x6Ah).
To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I2C transactions. If the transaction takes longer than
t_I2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
8.4.14.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 23. All I²C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 23. START and STOP Condition
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 24). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 24. Bit Transfer on the Serial Interface
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