TMS320VC5402_07 Datasheet, PDF (39/68 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
memory and parallel I/O interface timing
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t_c(CO)]^† (see Figure 13)
ta(A)M
Access time, read data access from address valid
ta(MSTRBL)
tsu(D)R
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
th(D)R
Hold time, read data after CLKOUT low
th(A-D)R
Hold time, read data after address invalid
th(D)MSTRBH Hold time, read data after MSTRB high
† _{Address, PS, and DS timings are all included in timings referenced as address.}
MIN MAX UNIT
2H–7 ns
2H–8 ns
6
ns
–2
ns
0
ns
0
ns
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)^† (see Figure 13)
PARAMETER
td(CLKL-A)
td(CLKH-A)
Delay time, CLKOUT low to address valid‡
Delay time, CLKOUT high (transition) to address valid§
td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low
td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high
th(CLKL-A)R Hold time, address valid after CLKOUT low‡
th(CLKH-A)R Hold time, address valid after CLKOUT high§
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{In the case of a memory read preceded by a memory read}
§ _{In the case of a memory read preceded by a memory write}
MIN MAX UNIT
–2
3 ns
–2
3 ns
–1
3 ns
–1
3 ns
–2
3 ns
–2
3 ns
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