TMS320VC5402_07 Datasheet, PDF (28/68 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME
DRR20
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DRR10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DXR20
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DXR10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _TIM
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _PRD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _TCR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ –
SWWSR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BSCR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SWCR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _HPIC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _TIM1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PRD1
TCR1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPSA0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPSD0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GPIOCR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GPIOSR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DRR21
DRR11
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DXR21
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DXR11
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPSA1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPSD1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DMPREC
DMSA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DMSDI
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DMSDN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _CLKMD
ADDRESS
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh–2Fh
30h
31h
32h
33h–37h
38h
39h
3Ah–3Bh
3Ch
3Dh
3Eh–3Fh
40h
41h
42h
43h
44h–47h
48h
49h
4Ah–53h
54h
55h
56h
57h
58h
DESCRIPTION
McBSP0 data receive register 2
McBSP0 data receive register 1
McBSP0 data transmit register 2
McBSP0 data transmit register 1
Timer0 register
Timer0 period counter
Timer0 control register
Reserved
Software wait-state register
Bank-switching control register
Reserved
Software wait-state control register
HPI control register
Reserved
Timer1 register
Timer1 period counter
Timer1 control register
Reserved
McBSP0 subbank address register†
McBSP0 subbank data register†
Reserved
General-purpose I/O pins control register
General-purpose I/O pins status register
Reserved
McBSP1 data receive register 2
McBSP1 data receive register 1
McBSP1 data transmit register 2
McBSP1 data transmit register 1
Reserved
McBSP1 subbank address register†
McBSP1 subbank data register†
Reserved
DMA channel priority and enable control register
DMA subbank address register‡
DMA subbank data register with autoincrement‡
DMA subbank data register‡
Clock mode register
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer0
Timer0
Timer0
External Bus
External Bus
External Bus
HPI
Timer1
Timer1
Timer1
McBSP #0
McBSP #0
GPIO
GPIO
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
DMA
DMA
DMA
DMA
PLL
–
59h–5Fh
Reserved
† _{See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.}
‡ _{See Table 12 for a detailed description of the DMA subbank addressed registers.}
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