TMS320VC5402_07 Datasheet, PDF (31/68 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.
NAME
RS, SINTR
NMI, SINT16
SINT17
SINT18
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT0, SINT3
BRINT0, SINT4
BXINT0, SINT5
Reserved(DMAC0), SINT6
TINT1(DMAC1), SINT7
INT3, SINT8
HPINT, SINT9
BRINT1(DMAC2), SINT10
BXINT1(DMAC3), SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
Table 13. Interrupt Locations and Priorities
LOCATION
DECIMAL
HEX
0
00
4
04
8
08
12
0C
16
10
20
14
24
18
28
1C
32
20
36
24
40
28
44
2C
48
30
52
34
56
38
60
3C
64
40
68
44
72
48
76
4C
80
50
84
54
88
58
92
5C
96
60
100
64
104
68
108
112
116
120–127
6C
70
74
78–7F
PRIORITY
1
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
FUNCTION
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer0 interrupt
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
Reserved (default) or DMA channel 0 inter-
rupt. The selection is made in the DMPREC
register.
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
External user interrupt #3
HPI interrupt
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
DMA channel 4 interrupt
DMA channel 5 interrupt
Reserved
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