DAC5682Z_15 Datasheet, PDF (39/66 Pages) Texas Instruments – DAC5682Z 16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)

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DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
8.6 Register Maps
The primary modes of operation, listed in Table 8, are selected by registers CONFIG1, CONFIG2, and
CONFIG3.
Table 8. DAC5682Z Modes of Operation
Mode
Name
1X1
(Bypass)
1X2
1X2 HP
1X4
1X4 LP/HP
1X4 HP/LP
1X4 HP/HP
2X1
2X2
2X2 HP
2X2 CMIX
2X4
2X4 LP/HP
2X4 CMIX
2X4 HP/LP
2X4 HP/HP
No. of
DACs
Out
1
Interp.
Factor
X1
FIR0,
CMIX0
Mode
–
FIR1,
CMIX1
Mode
–
Device
Config.
Single Real
1
X2
–
LP Single Real
1
X2
–
HP Single Real
1
X4
LP
LP Single Real
1
X4
LP
HP Single Real
1
X4
HP
LP Single Real
1
X4
HP
HP Single Real
2
X1
–
–
Dual Real
2
X2
–
LP Dual Real
2
X2
–
HP Dual Real
2
X2
–
LP,
Complex
Fs/4
2
X4
LP
LP Dual Real
2
X4
LP
HP Dual Real
2
X4
LP
LP,
Complex
Fs/4
2
X4
HP
LP Dual Real
2
X4
HP
HP Dual Real
LVDS
Input
Data
Mode
A
A
A
A
A
A
A
A/B
A/B
A/B
A/B
A/B
A/B
A/B
A/B
A/B
Max DCLK
Max CLKIN Freq [DDR]
Freq (MHz)⁽¹⁾
(MHz)
1000
500
Max Total
Input Bus
Rate
(MSPS)
1000
Max Input Data
Rate Per Chan
(#Ch @ MSPS)
1 at 1000
Max Signal
BW Per DAC
(MHz) ⁽²⁾
500
1000
250
500
1 at 500
200
1000
250
500
1 at 500
200
1000
125
250
1 at 250
100
1000
125
250
1 at 250
100
1000
125
250
1 at 250
50
1000
125
250
1 at 250
50
500
500
1000
2 at 500
250
1000
500
1000
2 at 500
200
1000
500
1000
2 at 500
200
1000
500
1000
2 at 500
200
1000
250
500
2 at 250
100
1000
250
500
2 at 250
100
1000
250
500
2 at 250
100
1000
250
500
2 at 250
50
1000
250
500
2 at 250
50
(1) Also the final DAC sample rate in MSPS.
(2) Assumes a 40% passband for FIR0 and/or FIR1 filters in all modes except 1X1 and 2X1 where simple Nyquist frequency is listed.
Slightly wider bandwidths may be achievable depending on filtering requirements. Refer to FIR Filters section for more detail on filter
characteristics. Also refer to Table 5 for IF placement and upconversion considerations.
Name
STATUS0
CONFIG1
CONFIG2
CONFIG3
STATUS4
CONFIG5
CONFIG6
CONFIG7
CONFIG8
CONFIG9
CONFIG10
CONFIG11
CONFIG12
CONFIG13
CONFIG14
CONFIG15
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Default
0x03
0x10
0xC0
0x70
0x00
0x00
0x0C
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Table 9. Register Map
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
PLL_lock
DLL_lock
Unused
device_ID(2:0)
version(1:0)
DAC_delay(1:0)
Unused
fir_ena
SLFTST _ena
FIFO_offset(2:0)
Twos_ comp
dual_DAC
FIR2x4x
Unused
CMIX1_mode(1:0)
CMIX0_mode(1:0)
DAC_offset _ena
SLFTST_err
_mask
FIFO_err_ mask
Pattern_err
_mask
SwapAB_ out
B_equals _A
SW_sync
SW_sync _sel
Unused
SLFTST_err
FIFO_err
Pattern_ err
Unused
Unused
Unused
Unused
SIF4
rev_bus clkdiv_ sync_dis Reserved
Reserved
DLL_ bypass
PLL_
bypass
Reserved
Reserved
Unused
Sleep_B
Sleep_A
BiasLPF_A
BiasLPF_B PLL_ sleep
DLL_ sleep
DACA_gain(3:0)
DACB_gain(3:0)
Reserved
DLL_ restart
Reserved
PLL_m(4:0)
PLL_n(2:0)
DLL_delay(3:0)
DLL_invclk
DLL_ifixed(2:0)
PLL_LPF _reset VCO_div2
PLL_gain(1:0)
PLL_range(3:0)
Reserved(1:0)
Offset_sync
OffsetA(12:8)
OffsetA(7:0)
SDO_func_sel(2:0)
OffsetB(12:8)
OffsetB(7:0)
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