DAC5682Z_15 Datasheet, PDF (24/66 Pages) Texas Instruments – DAC5682Z 16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)

DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
www.ti.com
FPGA / ASIC
SERDES
I
SERDES
D15
100
1.0 GBPS
(DDR)
D0
100
DAC5682Z DAC
DAC
5V
Term
5V
I-Signal
LPF
Q-Signal
TRF3703 AQM
PA
Q
DLL
SERDES
1.0 GHz
SERDES
4x Clock
Multiplier
DAC5682Z
Control
100
SYNC
100
DCLK ¹⁰⁰
500 MHz
Toggling
Data Bit
DLL
Control
DAC
opt.
PLL
Loop
Filter
Term
LPF
90 ₀
~ 2.1 GHz
250 MHz
Freq/Phase Locked
1.0 GHz
Term
CDCM7005
VCXO_STATUS
REF_STATUS
÷4
÷1
Clock Divider /
Distribution
Status &
Control
PLL
Synth
10 MHz
REF
OSC
REF_IN
Loop
Filter
VCXO
N-
Divider
R-
Div
To TX
Feedback
To RX
Path
TRF3761-X PLL/VCO
Div
1/2/4
VCO
VCTRL_IN
Loop
Filter
PFD
Charge
Pump
CPOUT
Status & Control
Antenna
CDCM7005
Control
PLL_LOCK
1000 MHz
TRF3761-X
Control
Figure 31. Example Direct Conversion System Diagram
From the example provided by Figure 32, driving LVDS data into the DAC using SERDES blocks requires a
parallel load of 4 consecutive data samples to shift registers. Color is used in the figure to indicate how data and
clocks flow from the FPGA to the DAC5682Z. The figure also shows the use of the SYNCP/N input, which along
with DCLK, requires 18 individual SERDES data blocks to drive the input data FIFO of the DAC that provides an
elastic buffer to the DAC5682Z digital processing chain.
24
Submit Documentation Feedback
Product Folder Links: DAC5682Z
Copyright © 2007–2015, Texas Instruments Incorporated