LM3S8538 Datasheet, PDF (374/590 Pages) Texas Instruments – Stellaris® LM3S8538 Microcontroller

Inter-Integrated Circuit (I²C) Interface
14.1 Block Diagram
Figure 14-1. I²C Block Diagram
Interrupt
I²C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICR
I²C Master Core
I2CSCL
I2CSDA
I²C Slave Core
I2CSCL
I2CSDA
I²C I/O Select
I2CSCL
I2CSDA
14.2
Functional Description
The I²C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I²C bus configuration is shown in Figure 14-2 on page 374.
See “Inter-Integrated Circuit (I²C) Interface” on page 556 for I²C timing diagrams.
Figure 14-2. I²C Bus Configuration
SCL
SDA
RPUP RPUP
I2C Bus
I2CSCL I2CSDA
StellarisTM
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
14.2.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris^®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
374
June 22, 2010
Texas Instruments-Production Data