LM3S8538 Datasheet, PDF (201/590 Pages) Texas Instruments – Stellaris® LM3S8538 Microcontroller

Stellaris® LM3S8538 Microcontroller
9.2
9.2.1
9.2.2
9.2.2.1
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 211),
the GPTM TimerA Mode (GPTMTAMR) register (see page 212), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 214). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 225) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 226). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 229) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 230).
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 225
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 226
■ GPTM TimerA (GPTMTAR) register [15:0], see page 233
■ GPTM TimerB (GPTMTBR) register [15:0], see page 234
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 212), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
June 22, 2010
201
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