TMS320C6421 Datasheet, PDF (37/59 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346A – JANUARY 2007 – REVISED MARCH 2007
Table 2-19. Multichannel Buffered Serial Port 0 (McBSP0) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
Multichannel Buffered Serial Port 0 (McBSP0)
Pin Muxing Control: TBD
CLKS0/TOUT0L/
GP[97]
J4
L3
I/O/Z
ACLKR0/CLKX0/
GP[99]
H1
J1
I/O/Z
AHCLKR0/CLKR0/
GP[101]
J2
K1
I/O/Z
AXR0[2]/FSX0/
GP[103]
H3
J2
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McBSP0, Timer0, and GPIO.
For McBSP0, it is McBSP0 external clock source (I).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit frame synchronization FSX0
(I/O/Z).
AXR0[3]/FSR0/
GP[102]
G4
J3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive frame synchronization FSR0
(I/O/Z).
AXR0[1]/DX0/
GP[104]
J3
K2
I/O/Z
AFSR0/DR0/
GP[100]
H4
K3
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data receive input DR0 (I).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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