TMS320C6421 Datasheet, PDF (27/59 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346A – JANUARY 2007 – REVISED MARCH 2007
Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEM[2:0], etc.). For more details, see ,
Multiplexed Pin Configurations.
EM_A[1]/(ALE)/
GP[9]/(PLLMS1)
A16
B20
I/O/Z
IPD
DV_DD33
This pin is multiplexed between EMIFA (NAND) and GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
EM_A[2]/(CLE)/
GP[8]/(PLLMS0)
B16
A20
I/O/Z
IPD
DV_DD33
This pin is multiplexed between EMIFA (NAND) and GPIO.
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
EM_WAIT/
(RDY/BSY)
EM_OE
EM_WE
E15 D20
D15 D19
E14 C19
I/O/Z
I/O/Z
I/O/Z
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
When used for EMIFA (NAND), this pin is read enable output (RE).
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_CS2/
GP[12]
C19 C22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_CS3/
GP[13]
C18 D22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use
with NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
RMRXD0/
EM_CS4/
GP[32]
E19 H22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
RMRXD1/
EM_CS5/
GP[33]
F19 J22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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