TLC320AD535C-I Datasheet, PDF (37/43 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

Appendix A
Programmable Register Set
Bits D12–D8 in a secondary serial communication comprise the address of the register that is written with data carried
in bits D7–D0. D13 determines a read or write cycle to the addressed register. When low (0), a write cycle is selected.
Table A–1 shows the register map.
Table A–1. Register Map
REGISTER NO. D15 D14 D13 D12 D11 D10 D9 D8 REGISTER NAME
0
0
0 R/W 0
0
0
0
0
No operation
1
0
0 R/W 0
0
0
0
1
Control 1
2
0
0 R/W 0
0
0
1
0
Control 2
3
0
0 R/W 0
0
0
1
1
Control 3
4
0
0 R/W 0
0
1
0
0
Control 4
5
0
0 R/W 0
0
1
0
1
Control 5
6
0
0 R/W 0
0
1
1
0
Control 6
D7 D6 D5 D4†
1 —— 0
0 —— 0
—1—0
—0—0
—— 1
0
—— 0
0
——— 0
——— 0
——— 0
——— 0
——— 0
——— 0
——— 0
——— 0
† _{D4 = reserved}
Default value: 00000000
Table A–2. Control Register 1, Data Channel Control
D3 D2 D1 D0
DESCRIPTION
— — — — Software reset for data channel asserted
— — — — Software reset for data channel not asserted
— — — — S/W power down for data channel enabled
— — — — S/W power down for data channel disabled
— — — — Data channel digital loopback asserted
— — — — Data channel digital loopback not asserted
1 — — — Select data_in PGA for monitor amp input
0 — — — Select DAC output for monitor amp input
— 1 — 1 Monitor amp PGA gain = 12 dB
—1
0 Monitor amp PGA gain = 9 dB
—0
1
1 Monitor amp PGA gain = 6 dB
—0
1
0 Monitor amp PGA gain = 3 dB
—0
0
1 Monitor amp PGA gain = 0 dB
—0
0
0 Monitor amp PGA gain = mute
A–1