TLC320AD535C-I Datasheet, PDF (15/43 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

2 Functional Description
2.1 Device Requirements and System Overview
The TLC320AD535 device consists of two codec channels, a hybrid circuit with external resistors and capacitors for
setting gain and filter poles, two independent serial ports, and other miscellaneous logic functions.
2.2 Codec Functions
The codec portion of the TLC320AD535 device performs the functions required for two channels of analog-to-digital
conversion, digital-to-analog conversion, lowpass filtering, control of analog input and output gains, internal
oversampling coupled with internal decimation and interpolation, and two 16-bit serial port interfaces to the host
processor. The two serial ports operate independently and are capable of operating at different sample rates. The
maximum sample rate of either codec channel is 11.025 kHz.
2.3 Hybrid Functions
The hybrid circuitry in the data channel includes integrated amplifiers whose gains and filter pole frequencies are set
by external resistors and capacitors. This allows maximum flexibility to make adjustments for board variations and
international standards while providing integration of the function. The filter amplifier stages in the data channel are
followed by a programmable gain amplifier, which feeds 8-Ω differential speaker drivers for the AT41 call progress
monitor speakers. The monitor speaker driver can be programmed for 0-dB gain or muted through the control 2
register. The source for the monitor speaker input can be either the output of the amplified DAC output (Data_Out
PGA) or the ADC input signal through control register 1 (See Appendix A).
A 2.5 V/1.5 V reference voltage (DT_REF) is provided as a reference for the transformer. It is necessary to reference
to 2.5 V/1.5 V (rather than ground), since the amplifiers are powered off by single-rail supplies. DT_REF is 2.5 V when
DAV_DD is 5 V and 1.5 V when DAV_DD is 3.3 V.
2.4 Voice Channel Analog
The analog circuitry in the voice channel includes a microphone bias, which sources a maximum of 5 mA at 2.5 V/
1.5 V, and preamplifiers for the microphone, which can be selected for 0-dB or 20-dB gain. The device also has a
handset interface with receive and transmit amplifiers. These three inputs can be summed in any combination and
the result sent to a Line_In programmable gain amplifier (PGA) stage with gain range from 12 dB to –36 dB in 1.5
dB noiseless steps. This feeds the voice channel ADC. In the DAC path, the output of the DAC is sent to a Line-Out
PGA with gain range from 12 dB to –36 dB in 1.5 dB noiseless steps. This feeds both a 600-Ω TAPI output driver and
a 60-Ω mono speaker driver that can be muted or programmed for 0-dB gain. The time-out for noiseless gain change
or the maximum time the system can wait for a zero crossing of a signal before it will effect the gain change request
is approximately 9 ms.
2.5 Miscellaneous Logic and Other Circuitry
The logic functions include the circuitry required to implement two independent serial ports and control register
programming through secondary communication on those serial ports. There are five control registers that are
programmed during secondary communications from either the data channel serial port or the voice channel serial
port. These control registers set amplifier gains, choose multiplexer inputs, select loopback functions, and read the
ADC overflow flags. The device also includes a power-on reset (POR) circuit to monitor the 5-V MV_DD power supply
in the system and provides a reset signal when the supply MV_DD voltage drops below its threshold voltage. In addition,
there is a flash write enable (FWE) circuit that takes an external logic input and provides 40 mA of current to power
the write enable circuit of an external memory device. The flash write enable circuit is powered from the digital power
supply.
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