TLC320AD535C-I Datasheet, PDF (17/43 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

3 Codec Functional Description
3.1 Operating Frequencies
The TLC320AD535 is capable of supporting any sample rate up to the maximum sample rate of 11.025 kHz in either
the data channel or voice channel. The sample rate is set by the frequency of the codec master clock that is input
to the serial port for that channel.
The sampling (conversion) frequency is derived from the internally-generated codec master clock divider circuit by
the following equation:
+ + ^ǒ ń ^Ǔ fs Sampling (conversion) frequency
+ ń XX_SCLK XX_MCLK 2
XX_MCLK 512
(1)
Where XX_MCLK refers to either the voice channel or data channel codec clock (VC_MCLK or DT_MCLK) fed to
the codec externally by the clock rate divider circuit. The clock rate divider circuit divides the system master clock
to obtain the necessary clock frequency to feed the codecs.
The inverse of the sampling frequency is the conversion period. The sample rates of the voice and data channels
can be set independently by their respective codec master clocks. The two codec channels can be sampled at
different rates simultaneously.
3.2 ADC Signal Channel
The input signals are amplified and filtered by on-chip buffers before being applied to their respective ADC input. In
the case of the voice channel, inputs from a microphone input and the handset input may be summed together before
being amplified/attenuated by the ADC line PGA. The ADC converts the signal into discrete output digital words in
2s-complement format, corresponding to the analog signal value at the sampling time. These 16-bit digital words,
representing sampled values of the analog input signal, are sent to the host through the serial port interface for their
respective channels. If the ADC reaches its maximum value, a control register flag is set. This overflow bit resides
at D0 in the data channel control register 2 or the voice channel control register 5. These bits can only be read from
their respective serial ports, and the overflow flag is cleared only if it is read through the voice channel serial port,
and similarly for the data channel. The ADC and DAC conversions are synchronous and phase-locked.
3.3 DAC Signal Channel
The DAC receives the 16-bit data words (2s complement) from the host through the serial port interface for each
channel. The data is converted to analog voltages by their respective sigma-delta DACs comprised of a digital
interpolation filter and a digital modulator. The outputs of the DACs are each then passed to internal low pass filters
to complete the signal reconstruction resulting in an analog signal. Those analog signals are then buffered and
amplified by an output driver capable of driving the required load. The gain of these output amplifiers is programmed
by the
+codec control registers, as shown in Appendix A.
3.4 Sigma-Delta ADC
Each ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and low noise performance
using oversampling techniques and the noise shaping advantages of sigma-delta modulators.
3.5 Decimation Filter
Each decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with a
ratio equal to the oversampling ratio. The output of this filter is a 16-bit 2s-complement data word clocking at the
selected sample rate.
3–1