TMS470R1A64PNTR Datasheet, PDF (36/46 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099B – NOVEMBER 2004 – REVISED AUGUST 2006
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
www.ti.com
Timing Requirements for Internal Clock SCIn Isosynchronous Mode^(1)(2)(3)
(see Figure 16)
t_c(SCC)
t_w(SCCL)
Cycle time, SCInCLK
Pulse duration,
SCInCLK low
t_w(SCCH)
Pulse duration,
SCInCLK high
t_d(SCCH-
TXV)
t_v(TX)
Delay time, SCInCLK
high to SCInTX valid
Valid time, SCInTX
data after SCInCLK low
t_su(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
t_v(SCCL-RX)
Valid time, SCInRX
data after SCInCLK low
(BAUD + 1)
IS EVEN OR BAUD = 0
MIN
MAX
2t_c(ICLK)
2²⁴ t_c(ICLK)
0.5t_c(SCC) – t_f
0.5t_c(SCC) + 5
0.5t_c(SCC) – t_r
0.5t_c(SCC) + 5
10
t_c(SCC) – 10
t_c(ICLK) + t_f + 20
–t_c(ICLK) + t_f + 20
(BAUD + 1)
IS ODD AND BAUD ≠ 0
MIN
MAX
3t_c(ICLK)
(2²⁴– 1) t_c(ICLK)
0.5t_c(SCC) + 0.5t_c(ICLK) – t_f 0.5t_c(SCC) + 0.5t_c(ICLK)
0.5t_c(SCC) – 0.5t_c(ICLK) – t_r 0.5t_c(SCC) – 0.5t_c(ICLK)
10
t_c(SCC) – 10
t_c(ICLK) + t_f + 20
–t_c(ICLK) + t_f + 20
(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(2) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table
UNIT
ns
ns
ns
ns
ns
ns
ns
t_c(SCC)
t_w(SCCL)
t_w(SCCH)
SCICLK
SCITX
SCIRX
t_{d(SCCHĆTXV)}
t_v(TX)
Data Valid
t_{su(RXĆSCCL)}
Data Valid
t_{v(SCCLĆRX)}
A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
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