TMS470R1A64PNTR Datasheet, PDF (25/46 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

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ZPLL AND CLOCK SPECIFICATIONS
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099B – NOVEMBER 2004 – REVISED AUGUST 2006
Timing Requirements for ZPLL Circuits Enabled or Disabled
f_(OSC)
t_c(OSC)
t_w(OSCIL)
t_w(OSCIH)
f_(OSCRST)
Input clock frequency
Cycle time, OSCIN
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency⁽¹⁾
MIN TYP
4
50
15
15
53
MAX
20
UNIT
MHz
ns
ns
ns
kHz
(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL[15]) and the OSC FAIL flag (GLBSTAT[1])
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
Switching Characteristics over Recommended Operating Conditions for Clocks⁽¹⁾⁽²⁾
PARAMETER
f_(SYS)
System clock frequency⁽⁴⁾
f_(CONFIG) System clock frequency - flash config mode
f_(ICLK)
Interface clock frequency
f_(ECLK) External clock output frequency for ECP Module
t_c(SYS)
Cycle time, system clock
t_c(CONFIG) Cycle time, system clock - flash config mode
t_c(ICLK) Cycle time, interface clock
t_c(ECLK) Cycle time, ECP module external clock output
TEST CONDITIONS⁽³⁾
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
MIN
MAX UNIT
48
MHz
24
24 MHz
25
MHz
24
25
MHz
24
20.8
ns
41.6
41.6
ns
40
ns
41.6
40
ns
41.6
(1) f_(SYS) = M × f_(OSC)/R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f_(SYS) = f_(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f_(ICLK) = f_(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2) f_(ECLK) = f_(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT[0]).
(4) Flash Vread must be set to 5V to achieve maximum system clock frequency.
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