TMS470R1A64PNTR Datasheet, PDF (35/46 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

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TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099B – NOVEMBER 2004 – REVISED AUGUST 2006
SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) ^(1)(2)(3)(4) (see Figure 15)
NO.
1
2 ⁽⁶⁾
3 ⁽⁶⁾
4 ⁽⁶⁾
5 ⁽⁶⁾
6 ⁽⁶⁾
7 ⁽⁶⁾
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
t_w(SPCL)S
t_w(SPCH)S
t_v(SOMI-
SPCH)S
t_v(SOMI-
SPCL)S
t_v(SPCH-
SOMI)S
t_v(SPCL-
SOMI)S
t_su(SIMO-
SPCH)S
t_su(SIMO-
SPCL)S
t_v(SPCH-
SIMO)S
t_v(SPCL-
SIMO)S
Cycle time, SPInCLK⁽⁵⁾
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
MIN
100
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 6 – t_r
0.5t_c(SPC)S – 6 – t_f
MAX
UNI
T
256t_c(ICLK)
ns
0.5t_c(SPC)S + 0.25t_{c(ICLK) ns}
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_{c(ICLK) ns}
0.5t_c(SPC)S + 0.25t_c(ICLK)
ns
0.5t_c(SPC)S – 6 – t_r
ns
0.5t_c(SPC)S – 6 – t_f
6
ns
6
6
ns
6
(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2[0]) is set.
(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S ≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(5) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(ICLK) ≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the clock polarity bit (SPInCTRL2[1]).
1
SPInCLK
(clock polarity = 0)
SPInCLK
(clock polarity = 1)
2
3
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
SPInSIMO
7
SPISIMO Data Must
Be Valid
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
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