ADS8363SRHBT Datasheet, PDF (36/49 Pages) Texas Instruments – Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter

ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
POWER-DOWN MODES AND RESET
These devices have a comprehensive built-in
power-down feature. There are three power-down
modes: Power-Down, Sleep, and Auto-Sleep
Power-Down. All three power-down modes are
activated with the completion of the write access,
during which the related bit(s) are asserted (PD[1:0]).
All modes are deactivated by deasserting the
respective bit(s) in the CONFIG register. The content
of the CONFIG register is not affected by any of the
power-down modes. Any ongoing conversion is
finished before entering any of the power-down
modes. Table 14 summarizes the differences among
the three power-down modes.
Power-Down Mode
In Power-Down mode (PD[1:0] = '01'), all functional
blocks except the digital interface are disabled. In this
mode, the current demand is reduced to 5µA within
20µs. The wakeup time from Power-Down mode is
8ms when using a reference capacitor of 22µF. The
device goes into Power-Down mode after completing
any ongoing conversions.
Sleep Mode
In Sleep mode (PD[1:0] = '10'), the device reduces its
current demand to approximately 0.9mA within 10µs.
The device goes into Sleep mode after completing
any ongoing conversions.
Auto-Sleep Mode
Auto-Sleep mode is almost identical to Sleep mode.
The only differences are the method of activating the
mode and waking up the device. CONFIG register
bits PD[1:0] = '11' are only used to enable/disable this
feature. If the Auto-Sleep mode is enabled, the
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device automatically turns off the biasing after
finishing a conversion; thus, the end of conversion
actually activates Auto-Sleep mode. If Sequencer
mode is used and individual conversion start pulses
are chosen (S1 = '0'), the device automatically
powers-down after each conversion; in case of a
single CONVST pulse starting the sequence (S1 =
'1'), power-down is activated upon completion of the
entire sequence.
The device wakes up with the next CONVST pulse
but the analog input is held in sample mode for
another seven clock cycles in half-clock mode, or 14
clock cycles in full-clock mode, before starting the
actual conversion (BUSY goes high thereafter), as
shown in Figure 41. This time is required to settle the
internal circuitry to the required voltage levels. The
conversion result is delayed in Auto-Sleep mode as
shown in Figure 39.
In this mode, the current demand is reduced to
approximately 1.2mA within 10µs.
Reset
To issue a device reset, an RD pulse must be
generated along with a control word containing A[3:0]
= '0100'. With the completion of this write access, the
entire device including the serial interface is forced
into reset, interrupting any ongoing conversions,
setting the input into acquisition mode, and returning
the register contents to their default values. After
~20ns, the serial interface becomes active again. The
device also supports an automatic power-up reset
(POR) that ensures proper (default) settings of the
device.
POWER-
DOWN MODE
Power-Down
Sleep
Auto-Sleep
POWER-
DOWN
CURRENT
5µA
1.2mA (3.6V)
1.2mA (3.6V)
Table 14. Power-Down Modes
POWER-
DOWN
ENABLED BY
PD[1:0] = '01'
PD[1:0] = '10'
PD[1:0] = '11'
POWER-
DOWN START
BY
Write access
completed
Write access
completed
Each end of
conversion
DELAY TIME
TO
POWER-
DOWN
20µs
10µs
10µs
NORMAL
OPERATION
BY
WAKEUP
TIME
POWER-
DOWN
DISABLED BY
PD[1:0] = '00'
8ms
PD[1:0] = '00'
PD[1:0] = '00'
7 or 14 CLOCK
cycles
CONVST pulse
7 or 14 CLOCK
cycles
PD[1:0] = '00'
PD[1:0] = '00'
36
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