ADS8363SRHBT Datasheet, PDF (17/49 Pages) Texas Instruments – Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter

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ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
Acquisition is indicated with the BUSY signal being
low. It starts by closing the input switches (after
finishing the previous conversion and precharging)
and finishes with the rising edge of the CONVST
signal. If the device operates at full speed, the
acquisition time is typically 100ns.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 16 for the resolution of the
ADS8363, n = 14 for the ADS7263, or n = 12 for the
ADS7223:
f_-3dB
=
ln(2)(n + 1)
2pt_ACQ
(1)
With t_ACQ = 100ns, the minimum bandwidth of the
driving amplifier is 19MHz for the ADS8363, 17MHz
for the ADS7263, and 15MHz for the ADS7223. The
required bandwidth can be lower if the application
allows a longer acquisition time.
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1.
However, linearity and THD are not directly affected
as a result of precharging the capacitors.
The OPA365 from Texas Instruments is
recommended as a driver; in addition to offering the
required bandwidth, it also provides a low offset and
excellent THD performance (see also Application
Information section).
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 100Ω
resistor (R_SER) is placed in series with the switch. The
switch resistance (R_SW) is typically 100Ω, as shown in
Figure 28).
An input driver may not be required, if the impedance
of the signal source (R_SOURCE) fulfills the requirement
of Equation 2:
R_SOURCE <
t_ACQ
C_Sln(2)(n + 1)
- (R_SER + R_SW)
Where:
n = 16/14/12 for the resolution of the
ADS8363/7263/7223, respectively.
C_S = 40pF sample capacitance.
R_SER = 100Ω input resistor value.
R_SW = 100Ω switch resistance value. (2)
With t_ACQ = 100ns, the maximum source impedance
should be less than 12Ω for the ADS8363, less than
40Ω for the ADS7263, and less than 77Ω for the
ADS7223. The source impedance can be higher if the
ADC is used at a lower data rate.
The differential input voltage range of the ADC is
±V_REF, the voltage at the selected REFIOx pin.
It is important to keep the voltage to all inputs within
the 0.3V limit below AGND and above AVDD, while
not allowing dc current to flow through the inputs
(exceeding these limits causes the internal ESD
diodes to conduct, leading to increased leakage
current that may damage the device). Current is only
necessary to recharge the sample-and-hold
capacitors.
Unused inputs should be directly tied to AGND or
RGND without the need of a pull-down resistor.
Analog-to-Digital Converters (ADCs)
The ADS8363/7263/7223 include two SAR-type,
1MSPS, 16-/14-/12-bit ADCs that include
sample-and-hold (S&H), respectively, as shown in the
Functional Block Diagram on the front page of this
data sheet.
CONVST
The analog inputs are held with the rising edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 12ns (minimum). The conversion
automatically starts with the rising CLOCK edge. A
rising edge of CONVST should not be issued during a
conversion (that is, when BUSY is high).
RD (read data) and CONVST can be shorted to
minimize necessary software and wiring. The RD
signal is triggered by the device on the falling edge of
CLOCK. Therefore, the combined signals must be
activated with the rising CLOCK edge. The
conversion then starts with the subsequent rising
CLOCK edge. In modes with only SDOA active (that
is, in modes II, IV, SII, and SIV), the maximum length
of the combined RD and CONVST signal is one clock
cycle if the half-clock timing is used.
If CONVST and RD are combined, CS must be low
whenever a new conversion starts; however, this
condition is not required if RD and CONVST are
controlled separately. Note that if FIFO is used,
CONVST must be controlled separately from RD.
After completing a conversion, the sample capacitors
are automatically precharged to the value of the
reference voltage used to significantly reduce the
crosstalk among the multiplexed input channels.
CLOCK
The ADS8363/7263/7223 use an external clock with
an allowable frequency range that depends on the
mode being used. By default (after power-up), the
ADC operates in half-clock mode, which supports a
clock in the range of 0.5MHz to 20MHz. In full-clock
mode, the ADC requires a clock in the range of 1MHz
to 40MHz. For maximum data throughput, the clock
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