ADS8363SRHBT Datasheet, PDF (19/49 Pages) Texas Instruments – Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter

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DIGITAL
This section reviews the timing and control of the
serial interface.
The ADS8363/7263/7223 offer a set of internal
registers (see the Register Map section for details),
which allows the control of several features and
modes of the device, as Table 5 shows.
Mode Selection Pin M0 and M1
The ADS8363/7263/7223 can be configured to four
different operating modes by using mode pins M0
and M1, as shown in Table 4.
Table 4. M0/M1 Truth Table
M0
M1
CHANNEL
SELECTION
SDOx USED
0
0 Manual (through SDI) SDOA and SDOB
0
1 Manual (through SDI)
SDOA only
1
0
Automatic
SDOA and SDOB
1
1
Automatic
SDOA only
The M0 pin sets either manual or automatic channel
selection. In Manual mode, CONFIG register bits
C[1:0] are used to select between channels CHx0
and CHx1. In Automatic mode, CONFIG register bits
C[1:0] are ignored and channel selection is controlled
by the device after each conversion. The automatic
channel selection is only performed on
fully-differential inputs in this case; for
pseudo-differential inputs, the internal sequencer
controls the input multiplexer.
The M1 pin selects between serial data being
transmitted simultaneously on both SDOA and SDOB
outputs for each channel, respectively, or using only
the SDOA output for transmitting data from both
channels (see Figure 34 through Figure 39 and the
associated text for more information).
Additionally, the SDI pin is used for controlling device
functionality through the internal register; see the
Register Map section for details.
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
Half-Clock Mode (default mode after power-up
and reset)
The ADS8363/7263/7223 power up in half-clock
mode, in which the ADC requires at least 20 CLOCKs
for a complete conversion cycle, including the
acquisition phase. The conversion result can only be
read during the next conversion cycle. The first output
bit is available with the falling RD edge, while the
following output data bits are refreshed with the rising
edge of CLOCK.
Full-Clock Mode (allowing conversion and data
readout within 1µs, supported in dual output
modes)
The full-clock mode allows converting data and
reading the result within 1µs. The entire cycle
requires 40 CLOCKs. The first output bit is available
with the falling RD edge while the following output
data bits are refreshed with the falling edge of the
CLOCK in this mode.
The full-clock mode can only be used with analog
power supply AVDD in the range of 4.5V to 5.5V and
digital supply DVDD in the range of 2.3V to 3.6V. The
internal FIFO is disabled in full-clock mode.
2-Bit Counter
These devices offers a selectable 2-bit counter
(activated using the CE bit in the CONFIG register)
that is a useful feature in safety applications. The
counter value automatically increments whenever a
new conversion result is stored in the output register,
indicating a new value. The counter default value
after power-up is '01' (followed by '10', '11', '00', '01',
and so on), as shown in Figure 31. Because the
counter value increments only when a new
conversion results are transferred to the output
register, this counter is used to verify that the ADC
has performed a conversion and the data read is the
result of this new conversion (not a old result read
multiple times).
INPUT SIGNAL TYPE
Fully-differential
(PDE bit = '0')
Pseudo-differential
(PDE bit = '1')
Table 5. Supported Operating Modes
MANUAL CHANNEL SELECTION
Operating modes: I, II, and special mode II
Channel information selectable through CID bit
FIFO: not available
Operating modes: I, II and special mode II
Channel information selectable through CID bit
FIFO: not available
AUTOMATIC CHANNEL SELECTION
Operating modes: III, IV and special mode IV
Channel information selectable through CID bit
FIFO: available in mode III and special mode IV;
when used, a single read pulse allows reading of all data
Operating modes: III and special mode IV
Channel information not available (CID bit forced to '1')
FIFO: available in mode III and special mode IV;
when used, a single read pulse allows reading of all data
Pseudo-differential sequencer is enabled
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Product Folder Link(s): ADS8363 ADS7263 ADS7223