SN65DSI85 Datasheet, PDF (35/45 Pages) Texas Instruments – MIPI DSI BRIDGE TO FLATLINK LVDS Dual Channel DSI to Dual-Link LVDS Bridge

www.ti.com
ADDRESS
0x3D
0x3E
SN65DSI85
SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012
Table 10. CSR Bit Field Definitions – Video Registers (continued)
BIT(S)
7:0
7:0
DESCRIPTION
RIGHT_CROP
This field controls the number of pixels removed from the beginning of the
active video line for DSI Channel B. This field only has meaning if
LEFT_RIGHT_PIXELS = ‘1’. This field defaults to 0x00. Note1: When the
SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field
is programmed to a value other than 0x00, the
CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to
the number of active pixels in the Right portion of the line after
RIGHT_CROP has been applied.
LEFT_CROP
This field controls the number of pixels removed from the end of the active
video line for DSI Channel A. This field only has meaning if
LEFT_RIGHT_PIXELS = ‘1’. This field defaults to 0x00. Note1: When the
SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field
is programmed to a value other than 0x00, the
CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to
the number of active pixels in the Left portion of the line after LEFT_CROP
has been applied.
DEFAULT
0
0
ACCESS ⁽¹⁾
RW
RW
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: SN65DSI85
Submit Documentation Feedback
35