SN65DSI85 Datasheet, PDF (27/45 Pages) Texas Instruments – MIPI DSI BRIDGE TO FLATLINK LVDS Dual Channel DSI to Dual-Link LVDS Bridge

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SN65DSI85
SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012
ADDRESS
0x18
BIT(S)
7
6
5
4
3
2
1
0
Table 9. CSR Bit Field Definitions – LVDS Registers
DESCRIPTION
DE_NEG_POLARITY
0 – DE is positive polarity driven ‘1’ during active pixel transmission on LVDS
(default)
1 – DE is negative polarity driven ‘0’ during active pixel transmission on
LVDS
HS_NEG_POLARITY
0 – HS is positive polarity driven ‘1’ during corresponding sync conditions
1 – HS is negative polarity driven ‘0’ during corresponding sync (default)
VS_NEG_POLARITY
0 – VS is positive polarity driven ‘1’ during corresponding sync conditions
1 – VS is negative polarity driven ‘0’ during corresponding sync (default)
LVDS_LINK_CFG
0 – LVDS Channel A and Channel B outputs enabled
When CSR 0x10.6:5 = ’00’ or ‘01’, the LVDS is in Dual-Link
configuration
When CSR 0x10.6:5 = ‘10’, the LVDS is in two Single-Link configuration
1 – LVDS Single-Link configuration; Channel A output enabled and Channel
B output disabled (default)
CHA_24BPP_MODE
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled
CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled
CHA_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits
(MSB) per color; Format 2 (default)
1 – LVDS channel B lane B_Y3P/N transmits the 2 least significant bits (LSB)
per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the SN65DSI85
will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In
this configuration, the SN65DSI85 will not transmit the 2 LSB per color on
LVDS channel A, since LVDS channel A lane 4 is disabled.
CHB_24BPP_FORMAT1
This field selects the 24bpp data format
0 – Data lane 4 transmits the 2 most significant bits (MSB) per color; Format
2 (default)
1 – Data lane 4 transmits the 2 least significant bits (LSB) per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHB_24BPP_MODE is ‘0’, the SN65DSI85
will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In
this configuration, the SN65DSI85 will not transmit the 2 LSB per color on
LVDS channel B, since LVDS channel B lane 4 is disabled.
DEFAULT
0
1
1
1
0
0
0
0
ACCESS ⁽¹⁾
RW
RW
RW
RW
RW
RW
RW
RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
Copyright © 2012, Texas Instruments Incorporated
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