SN65DSI85 Datasheet, PDF (33/45 Pages) Texas Instruments – MIPI DSI BRIDGE TO FLATLINK LVDS Dual Channel DSI to Dual-Link LVDS Bridge

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ADDRESS
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
SN65DSI85
SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012
Table 10. CSR Bit Field Definitions – Video Registers (continued)
BIT(S)
3:0
7:0
3:0
7:0
1:0
7:0
1:0
7:0
1:0
DESCRIPTION
CHA_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set
to 01 or 00(CSR 0x10.6:5).. The delay specified by this field is in addition to
the pipeline and synchronization delays in the SN65DSI85. The additional
delay is approximately 10 pixel clocks. The Sync delay must be programmed
to at least 32 pixel clocks to ensure proper operation. The value in this field is
the upper 4 bits of the 12-bit value for the Sync delay.
CHB_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
Channel B when the SN65DSI85 is configured as two single stream mode
with CSR 0x18.4=0 and CSR 0x10.6:5 = ‘10’. The delay specified by this field
is in addition to the pipeline and synchronization delays in the SN65DSI85.
The additional delay is approximately 10 pixel clocks. The Sync delay must
be programmed to at least 32 pixel clocks to ensure proper operation. The
value in this field is the lower 8 bits of the 12-bit value for the Sync delay
CHB_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
Channel B when the SN65DSI85 is configured as two single stream mode
with CSR 0x18.4=0 and CSR 0x10.6:5 = ‘10’. The delay specified by this field
is in addition to the pipeline and synchronization delays in the SN65DSI85.
The additional delay is approximately 10 pixel clocks. The Sync delay must
be programmed to at least 32 pixel clocks to ensure proper operation. The
value in this field is the upper 4 bits of the 12-bit value for the Sync delay.
CHA_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A
and B in dual LVDS Channel mode(CSR 0x18.4=0) with
DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field
is the lower 8 bits of the 10-bit value for the HSync Pulse Width.
CHA_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A
and B in dual LVDS Channel mode(CSR 0x18.4=0) with
DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field
is the upper 2 bits of the 10-bit value for the HSync Pulse Width.
CHB_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel B. The value in this field is the lower 8 bits of the 10-bit value
for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 =
‘10’.
CHB_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel B. The value in this field is the upper 2 bits of the 10-bit value
for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 =
‘10’.
CHA_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync Pulse Width for LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set
to 01 or 00(CSR 0x10.6:5). The value in this field is the lower 8 bits of the 10-
bit value for the VSync Pulse Width.
CHA_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync Pulse Width for LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set
to 01 or 00(CSR 0x10.6:5). The value in this field is the upper 2 bits of the
10-bit value for the VSync Pulse Width.
DEFAULT
0
0
0
0
0
0
0
0
0
ACCESS ⁽¹⁾
RW
RW
RW
RW
RW
RW
RW
RW
RW
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