BQ27505-J4 Datasheet, PDF (34/38 Pages) Texas Instruments – System-Side Impedance Track™ Fuel Gauge

bq27505-J4
SLVSA40 – DECEMBER 2009
www.ti.com
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a
register internal to the I²C communication engine, will increment whenever data is acknowledged by the
bq27505-J4 or the I²C master. “Quick writes” function in the same manner and are a convenient means of
sending multiple bytes to consecutive command locations (such as two-byte commands that require two
bytes of data).
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
7.2 I²C Time Out
The I²C engine will release both SDA and SCL if the I2C bus is held low for about 2 seconds. If the
bq27505-J4 was holding the lines, releasing them will free for the master to drive the lines. If an external
condition is holding either of the lines low, the I²C engine will enter the low power sleep mode.
To make sure the correct results of a command with the 400kHz I²C operation, a proper waiting time
should be added between issuing command and reading results. For subcommands, the following
diagram shows the waiting time required between issuing the control command the reading the status with
the exception of checksum and OCV commands. A 100ms waiting time is required between the checksum
command and reading result, and a 1.2 second waiting time is required between the OCV command and
result. For read-write standard command, a minimum of 2 seconds is required to get the result updated.
For read-only standard commands, there is no waiting time required, but the host should not issue all
standard commands more than two times per second. Otherwise, the gauge could result in a reset issue
due to the expiration of the watchdog timer.
The I²C clock stretch could happen in a typical application. A maximum 80ms clock stretch could be
observed during the flash updates. There is up to 270ms clock stretch after the OCV command is issued.
S ADDR [6:0] 0 A
S ADDR [6:0] 0 A
CMD [7:0]
CMD [7:0]
A DATA [7:0] A DATA [7:0] A P 66ms
A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0]
Waiting time between control subcommand and reading results
N P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] N P 66ms
Waiting time between continuous reading results
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COMMUNICATIONS
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