AM5728_15 Datasheet, PDF (335/415 Pages) Texas Instruments – AM572x SitaraTM Processors

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AM5728, AM5726
SPRS915O – MARCH 2014 – REVISED OCTOBER 2015
(1) i in [i:0] = 3
Table 7-113. Switching Characteristics for MMC4 - Default Speed Mode ⁽²⁾
NO. PARAMETER
DESCRIPTION
DS0 fop(clk)
Operating frequency, mmc4_clk
DS1
DS2
DS3
DS4
t_w(clkH)
t_w(clkL)
t_d(clkL-cmdV)
t_d(clkL-dV)
Pulse duration, mmc4_clk high
Pulse duration, mmc4_clk low
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
MIN
0.45*P ⁽¹⁾
0.45*P ⁽¹⁾
-9.61
-9.61
MAX
24
9.61
9.61
UNIT
MHz
ns
ns
ns
ns
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
DS2
DS1
DS0
DS6
DS5
DS8
DS7
Figure 7-83. MMC/SD/SDIOj in - Default Speed - Receiver Mode
vayu_mmc3_07
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
DS2
DS1
DS0
DS3
DS4
Figure 7-84. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
vayu_mmc3_08
7.23.3.2 MMC3 and MMC4, SD High Speed
Figure 7-85, Figure 7-86, and Table 7-114 through Table 7-117 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter
mode.
Table 7-114. Timing Requirements for MMC3 - SD/SDIO High Speed Mode ⁽¹⁾
NO.
HS3
HS4
HS7
HS8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
MAX UNIT
5.33
ns
2.50
ns
5.33
ns
2.50
ns
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Timing Requirements and Switching Characteristics 335
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