AM5728_15 Datasheet, PDF (320/415 Pages) Texas Instruments – AM572x SitaraTM Processors

AM5728, AM5726
SPRS915O – MARCH 2014 – REVISED OCTOBER 2015
www.ti.com
Table 7-92. Timing Requirements for MMC1 - SD Card SDR50 Mode (continued)
NO. PARAMETER
SDR50 t_su(dV-clkH)
7
SDR50 t_h(clkH-dV)
8
DESCRIPTION
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
Pad Loopback Clock
Internal Loopback Clock
MIN MAX UNIT
1.41
ns
1.96
ns
1.6
ns
Table 7-93. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO. PARAMETER
SDR501 fop(clk)
SDR502 t_w(clkH)
H
SDR502L t_w(clkL)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
SDR505 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
SDR506 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-2.68
-2.68
MAX
96
UNIT
MHz
ns
ns
1.22 ns
1.41 ns
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR501
SDR502L
SDR503
SDR507
SDR502H
SDR504
SDR508
Figure 7-69. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
vayu_mmc1_09
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR501
SDR502H
SDR502L
SDR505
SDR506
SDR505
SDR506
Figure 7-70. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
vayu_mmc1_10
7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle
Table 7-94 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver
and transmitter mode (see Figure 7-71 and Figure 7-72)
Table 7-94. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO. PARAMETER
SDR1041 fop(clk)
SDR1042 t_w(clkH)
H
SDR1042 t_w(clkL)
L
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
MAX
192
UNIT
MHz
ns
ns
320 Timing Requirements and Switching Characteristics
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