THS7353 Datasheet, PDF (33/51 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

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APPLICATION INFORMATION (continued)
THS7353
SLOS484 – NOVEMBER 2005
Y’
HDTV
480i
576i
480p
576p ^P’B
720p
1080i
1080p
G’B’R’ ^P’R
CBVS
S-Video Y’
S-Video C’
External
Input
0.1 mF
75 W
1 mF
75 W
1 mF
75 W
0.1 mF
75 W
0.1 mF
75 W
0.1 mF
75 W
THS7353
1
AC STC
2
AC BIAS
3
AC BIAS
4
AC STC
5
AC STC
6
AC BIAS
7
NC
CH.1 IN A
CH.2 IN A
CH.3 IN A
CH.1 IN B
CH.2 IN B
CH.3 IN B
NC 20
CH.1 OUT 19
CH1. ₁₈
GAIN ADJ
CH.2 OUT 17
CH2.
GAIN ADJ
16
CH.3 OUT 15
CH3.
GAIN ADJ
14
8 I 2C-A1
I2C-SCL 13
V_{S+ 9 I 2C-A0}
10 GND
I2C-SDA 12
V_S+ 11
0.01 mF
2
I C Address = 0101101X
3.3 V
C_I
Ch. 1
C_I
Ch. 2
C_I
Ch. 3
3.3 V
+
100 mF
2
IC
Controller
R
(130 W)
DC + 135 mV
THS7303
470 mF
(See Note A)
+
Y’
Out
75 W
DAC /
Encoder
3.3 V
Y’
P’_B
P’_R
R
(130 W)
R
(130 W)
Y’
P’_B
P’_R
0.1 mF
75 W
1 mF
1 NC
NC 20
2 CH.1 IN A
DC + 135 mV
3 CH.2 IN A
DC + 135 mV
4 CH.3 IN A
AC STC
5 CH.1 IN B
AC Bias
6 CH.2 IN B
AC Bias
7 CH.3 IN B
CH.1 OUT 19
CH.1 SAG 18
CH.2 OUT 17
CH.2 SAG 16
CH.3 OUT 15
CH.3 SAG 14
8 I2C-A1
SCL 13
9 I2C-A0
10 GND
SDA 12
VS+ 11
75 W
1 mF
0.01 mF
2
I C Address = 0101100X
470 mF
P’_B
(See Note A)
+
75 W
Out
470 mF
P’_R
(See Note A) _{75 W} ^Out
+
3.3 V
+
100 mF ₂
IC
Controller
75 W
75 W
75 W
CVBS
S-Video
Y’
S-Video
C’
External
Input
R
(130 W)
75 W
DC + 135 mV
THS7313
R
(130 W)
R
(130 W)
CBVS
S-Video Y’
0.1 mF
75 W
0.1 mF
1 NC
NC 20
2 CH.1 IN A
DC + 135 mV
3 _{CH.2 IN A}
DC + 135 mV
4 CH.3 IN A
AC STC
5 CH.1 IN B
AC Bias
6 CH.2 IN B
AC Bias
7 _{CH.3 IN B}
+V_S 8 I2C-A1
CH.1 OUT 19
CH.1 SAG 18
CH.2 OUT 17
CH.2 SAG 16
CH.3 OUT 15
CH.3 SAG 14
SCL 13
9 I2C-A0
10 GND
SDA 12
V_S+ 11
75 W
0.1 mF
0.1 mF
2
I C Address = 0101110X
S-Video C’
External
Input
75 W
470 mF
(See Note A)
+
75 W
CBVS
Out
470 mF
(See Note A)
+
75 W
Y’
Out
S-Video
0.1 mF
C’
Out
75 W
3.3 V
+
100 mF
2
IC
Controller
75 W
75 W
75 W
A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-µF capacitor
in parallel with these large capacitors.
Figure 69. Typical SD/ED/HD System Interfacing with a THS7353, THS7303, and THS7313
33