THS7353 Datasheet, PDF (23/51 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

www.ti.com
APPLICATION INFORMATION (continued)
Input
V_S+
Input
Pin
Internal
Circuitry
THS7353
SLOS484 – NOVEMBER 2005
Figure 60. Equivalent DC Input Mode Circuit
The input stage of the THS7353 is designed with PNP bipolar transistors. Thus, there is a finite amount of bias
current flowing out of the THS7353 input pin. This bias current, typically about 0.6 µA, must have a path to flow
or else the input stage voltage increases. For example, if there is a 1-MΩ resistance to ground on the input node,
the resulting voltage appearing at the input node is 0.6 µA x 1 MΩ = 0.6 V. Therefore, it should be noted that if a
channel is powered on and has no input termination, the input bias current causes the input stage to float high
until saturation of the input stage exists - about 1.4 V from the power supply. Typically, this is not a concern as
most terminations result in an equivalent source impedance of 37.5 Ω if connected or 75 Ω if unconnected.
INPUT MODES OF OPERATION – DC + 250 mV SHIFT
Output clipping occurs with a 0-V applied input signal when the input mode is set to dc. The clipping can reduce
the sync amplitudes (both horizontal and vertical sync amplitudes) on the video signal. A problem occurs if the
receiver of this video signal uses an AGC loop to account for losses in the transmission line. Some video AGC
circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC
circuit can increase the gain too much, resulting in too much luma and/or chroma amplitude gain correction. This
may result in a picture with an overly bright display with too much color saturation.
Other AGC circuits use the chroma burst amplitude for amplitude control, and a reduction in the sync signals
does not alter the proper gain setting. But, it is good engineering design practice to ensure saturation/clipping
does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation
could possibly result in timing delays or other aberrations on the signals.
To eliminate saturation / clipping problems, the THS7353 has a dc + 250 mV shift input mode. This mode takes
the input voltage and adds an internal +250 mV shift to the signal. This shift cannot be measured at the input pin
because it is internal, thus, it does not impact the source in any way. Because the THS7353 also has a default
gain of 0 dB (1 V/V), the resulting output with a 0-V applied input signal is 250 mV. The THS7353 rail-to-rail
output stage creates this level while connected to a typical load. This ensures that no saturation / clipping of the
sync signals occurs. This is a constant shift regardless of the input signal. For example, if a 1-V is applied to the
input the output is at 1.25 V.
As with the dc-input mode, the input impedance of the THS7353 is > 1 MΩ. Additionally, the same input bias
current of about 0.6 µA appears at the input. Following the same precautions as stipulated with the dc-input
mode of operation minimizes any potential issues. Figure 61 shows the equivalent input circuit while in the dc +
250 mV shift mode of operation.
23