DAC3283_15 Datasheet, PDF (33/67 Pages) Texas Instruments – DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)

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DAC3283
SLAS693C – MARCH 2010 – REVISED MARCH 2015
DACCLKP
OSTRP
DACCLKN
OSTRN
CLKVDD
500 W
2 kW
2 kW
500 W
Note: Input common mode level is
approximately 1/2*CLKVDD18,
or 0.9V nominal.
GND
Figure 44. DACCLKP/N and OSTRP/N Equivalent Input Circuit
Figure 45 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
Differential ⁺
ECL
or
(LV )PECL
source _-
0.1 mF
CLKIN
C_AC
100 W
150 W
0.1 mF
R_T
150 W
CLKINC
Figure 45. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source
8.4.16 LVDS INPUTS
The D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 46.
Figure 47 shows the typical input levels and common-move voltage used to drive these inputs.
To Adjacent
LVDS Input
D[7:0]P,
DATACLKP ,
FRAMEP
Ref Note (1)
100 pF
Total
D[7:0]N,
DATACLKN ,
FRAMEN
To Adjacent
LVDS Input
LVDS
Receiver
Note (1): RCENTER node common
to the D[7:0]P/N, DATACLKP /N and
FRAMEP/N receiver inputs
Figure 46. D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS Input Configuration
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