DAC3283_15 Datasheet, PDF (17/67 Pages) Texas Instruments – DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)

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DAC3283
SLAS693C – MARCH 2010 – REVISED MARCH 2015
Feature Description (continued)
8.3.1.4 Gain Drift
Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at
ambient (25°C) to values over the full operating temperature range.
8.3.1.5 Gain Error
Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the
ideal full-scale output current.
8.3.1.6 Integral Nonlinearity (INL)
Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
8.3.1.7 Intermodulation Distortion (IMD3, IMD)
The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of the worst 3rd-order (or higher)
intermodulation distortion product to either fundamental output tone.
8.3.1.8 Offset Drift
Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at
ambient (25°C) to values over the full operating temperature range.
8.3.1.9 Offset Error
Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and the
ideal mid-scale output current.
8.3.1.10 Output Compliance Range
Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this
limit may result reduced reliability of the device or adversely affecting distortion performance.
8.3.1.11 Reference Voltage Drift
Defined as the maximum change of the reference voltage in ppm per degree Celsius from value at ambient
(25°C) to values over the full operating temperature range.
8.3.1.12 Spurious Free Dynamic Range (SFDR)
Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal.
8.3.1.13 Noise Spectral Density (NSD)
Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal power
and the noise floor of 1Hz bandwidth within the first Nyquist zone.
8.4 Device Functional Modes
8.4.1 Serial Interface
The serial port of the DAC3283 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC3283. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface by sif4_ena in register CONFIG23. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is bidirectional and ALARM_SDO is data out only. Data is input into
the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
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