ADS58J63_15 Datasheet, PDF (33/84 Pages) Texas Instruments – ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device

www.ti.com
ADS58J63
SBAS717A – JUNE 2015 – REVISED JUNE 2015
7.4.12 Power-Down Mode
The ADS58J63 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured, which allows a trade-off between wake-up time and power consumption
in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2 as shown
in Table 10. See the master page registers in Table 15 for further details.
Table 10. Register Address for Power-Down Modes
REGISTER
ADDRESS
COMMENT
REGISTER DATA
A[7:0] (Hex)
7
6
5
4
3
2
1
0
MASTER PAGE (80h)
20
PDN ADC CHAB
PDN ADC CHCD
MASK 1
21
PDN BUFFER CHCD
PDN BUFFER CHAB
0
0
0
0
23
PDN ADC CHAB
PDN ADC CHCD
MASK 2
24
PDN BUFFER CHCD
PDN BUFFER CHAB
0
0
0
0
26
CONFIG
GLOBAL
PDN
OVERRIDE PDN MASK
PDN PIN
SEL
0
0
0
0
0
53
0
MASK
SYSREF
0
0
0
0
0
0
55
0
0
0
PDN MASK
0
0
0
0
To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,
when JESD link must remain up while putting the device in power down, the ADC and analog buffer can be
powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK
register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 11
shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx
register bits.
REGISTER BIT
Default
GBL PDN = 1
GBL PDN = 0,
PDN ADC CHx = 1
(x = AB or CD)
GBL PDN = 0,
PDN BUFF CHx = 1
(x = AB or CD)
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = AB or CD)
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = AB and CD)
Table 11. Power Consumption in Different Power-Down Settings
COMMENT
After reset, with a full-scale input signal to
both channels
The device is in complete power-down
state
The ADCs of one pair of channels are
powered down
IAVDD3V
(mA)
0.340
0.002
0.277
The input buffers of one pair of channels
iarepowered down
0.266
IAVDD
(mA)
0.365
0.006
0.225
0.361
IDVDD
(mA)
0.184
0.012
0.123
0.187
IIOVDD
(mA)
0.533
0.181
0.496
0.527
The ADCs and input buffers of one pair of
channels are powered down
0.200
0.224
0.126
0.492
The ADCs and input buffers of all channels
are powered down
0.060
0.080
0.060
0.448
TOTAL
POWER
(W)
2.675
0.247
2.063
2.445
1.830
0.960
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS58J63
Submit Documentation Feedback
33