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ADS58J63_15 Datasheet, PDF (1/84 Pages) Texas Instruments – ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device | |||
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ADS58J63
SBAS717A â JUNE 2015 â REVISED JUNE 2015
ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device
1 Features
â¢1 Quad Channel
⢠14-Bit Resolution
⢠Maximum Clock Rate: 500 MSPS
⢠Input Bandwidth (3 dB): 900 MHz
⢠On-Chip Dither
⢠Analog Input Buffer with High-Impedance Input
⢠Output Options:
â Rx: Decimate-by-2 and -4 Options with Low-
Pass Filter
â 200-MHz Complex Bandwidth or 100-MHz
Real Bandwidth Support
â DPD FB: Burst Mode with 14-Bit Output
⢠1.9-VPP Differential Full-Scale Input
⢠JESD204B Interface:
â Subclass 1 Support
â 1 Lane per ADC Up to 10 Gbps
â Dedicated SYNC pin for pair of channels
⢠Support for Multi-Chip Synchronization
⢠72-Pin VQFN Package (10 mm à 10 mm)
⢠Key Specifications:
â Power Dissipation: 675 mW/ch
â Spectral Performance (Un-decimated)
â fIN = 190 MHz IF at â1 dBFS:
â SNR: 70.4 dBFS
â NSD: â154.4 dBFS/Hz
â SFDR: 86 dBc (HD2, HD3),
95 dBFS (non HD2, HD3)
â fIN = 370 MHz IF at â3 dBFS:
â SNR: 68.5 dBFS
â NSD: â152.5 dBFS/Hz
â SFDR: 81 dBc (HD2, HD3),
86 dBFS (non HD2, HD3)
2 Applications
⢠Multi-Carrier GSM Cellular Infrastructure Base
Stations
⢠Multi-Carrier Multi-Mode Cellular Infrastructure
Base Stations
⢠Telecommunications Receiver
⢠Telecom DPD Observation Receiver
3 Description
The ADS58J63 is a low-power, wide-bandwidth, 14-
bit, 500-MSPS, quad-channel, telecom receiver
device. The ADS58J63 supports a JESD204B serial
interface with data rates up to 10 Gbps with one lane
per channel. The buffered analog input provides
uniform input impedance across a wide frequency
range and minimizes sample-and-hold glitch energy.
The ADS58J63 provides excellent spurious-free
dynamic range (SFDR) over a large input frequency
range with very low power consumption. The digital
signal processing block includes complex mixers
followed by low-pass filters with decimate-by-2 and -4
options supporting up to 200-MHz receive bandwidth.
The ADS58J63 also supports a 14-bit, 500-MSPS
output in burst-mode making the device suitable for a
DPD observation receiver.
The JESD204B interface reduces the number of
interface lines, thus allowing high system integration
density. An internal phase locked loop (PLL)
multiplies the incoming analog-to-digital converter
(ADC) sampling clock to derive the bit clock, which is
used to serialize the 14-bit data from each channel.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS58J63
VQFN (72)
10.00 mm x 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
INAP/M
INBP/M
SYSREFP/M
CLKINP/M
INCP/M
INDP/M
Simplified Block Diagram
14bit
ADC
14bit
ADC
Digital Block
Interleaving
Correction
Digital Block
Interleaving
Correction
2x
FS/4
4x
2x
K*FS/16
FS/8
Burst Mode
JESD204B
PLL
x10/x20
14bit
ADC
14bit
ADC
Digital Block
Interleaving
Correction
Digital Block
Interleaving
Correction
Burst Mode
2x
FS/4
4x
2x
K*FS/16
FS/8
Configuration
Registers
JESD204B
DAP/M
DBP/M
TRIGAB
TRIGCD
TRDYAB
TRDYCD
SYNCbAB
SYNCbCD
DCP/M
DDP/M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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