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DAC8164 Datasheet, PDF (32/47 Pages) Texas Instruments – 14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference | |||
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DAC8164
SBAS410A â FEBRUARY 2008 â REVISED FEBRUARY 2008 ......................................................................................................................................... www.ti.com
Example 3: Power-Down DAC A and DAC B to 1k⦠and Power-Down DAC C and DAC D to 100kâ¦
Simultaneously
⢠1st: Write power-down command to data buffer A: DAC A to 1kâ¦.
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
1
DB15
0
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠2nd: Write power-down command to data buffer B: DAC B to 1kâ¦.
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
1
DB15
0
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠3rd: Write power-down command to data buffer C: DAC C to 100kâ¦.
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
1
DB15
1
DB14
0
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠4th: Write power-down command to data buffer D: DAC D to 100k⦠and simultaneously update all DACs.
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
1
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
1
DB15
1
DB14
0
DB13 DB12-DB2 DB1-DB0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
⢠1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
1
DB15
1
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
1
DB15
1
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
1
DB15
1
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
⢠4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23
(A1)
0
DB22
(A0)
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
1
DB15
1
DB14
1
DB13 DB12-DB2 DB1-DB0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
32
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