DAC8164 Datasheet, PDF (28/47 Pages) Texas Instruments – 14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8164
SBAS410A – FEBRUARY 2008 – REVISED FEBRUARY 2008 ......................................................................................................................................... www.ti.com
LD1 (DB21) and LD0 (DB20) control the loading of
each analog output with the specified 14-bit data
value or power-down command. Bit DB19 must
always be '0'. The DAC channel select bits (DB18,
DB17) control the destination of the data (or
power-down command) from DAC A through DAC D.
The final control bit, PD0 (DB16), selects the
power-down mode of the DAC8164 channels as well
as the power-down mode of the internal reference.
The DAC8164 supports a number of different load
commands. The load commands include broadcast
commands to address all the DAC8164s on an SPI
bus. The load commands are summarized as follows:
DB21 = 0 and DB20 = 0: Single-channel store. The
data buffer corresponding to a DAC selected by
DB18 and DB17 updates with the contents of SR
data (or power-down).
DB21 = 0 and DB20 = 1: Single-channel update.
The data buffer and DAC register corresponding to a
DAC selected by DB18 and DB17 update with the
contents of SR data (or power-down).
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from data buffers.
DB21 = 1 and DB20 = 1: Broadcast update. All the
DAC8164s on the SPI bus respond, regardless of
address matching. If DB18 = 0, SR data are ignored
and any channels from all DAC8164s update with
previously stored data (or power-down). If DB18 = 1,
SR data (or power-down) update any channels of all
DAC8164s in the system. This broadcast update
feature allows the simultaneous update of up to 16
channels.
Refer to Table 5 for more information.
Table 5. Control Matrix for the DAC8164
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13-DB2
A1
A0 LD 1 LD 0
0
DAC Sel 1 DAC Sel 0 PD0 MSB MSB-1 MSB-2...LSB
(Address Select)
0/1
0/1
See Below
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0 and A1 should
correspond to the 0
1
0
package address
set via pins 13
and 14
0
1
0
0
0
0
1
1
0
1
1
(00, 01, 10, or 11)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
0
Data
0
Data
0
Data
0
Data
1
See Table 6
0
0
Data
1
See Table 6
0
1
0
0
(00, 01, 10, or 11)
0
Data
1
0
0
X
X
1
1
0
X
X
1
1
0
X
X
1
1
0
(00, 01, 10, or 11)
1
Broadcast Modes
0
X
X
1
X
0
1
X
1
See Table 6
0
X
Data
See Table 6
0
DB1-DB0
Don't
Care
X
X
X
X
X
X
X
X
X
DESCRIPTION
This address selects one of four possible
devices on a single SPI data bus based on the
address pin(s) state of each device.
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
Write to buffer (selected by DB17 and DB18)
with power-down command
Write to buffer with data and load DAC
(selected by DB17 and DB18)
Write to buffer with power-down command and
load DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and
DB18) and then load all DACs simultaneously
from their corresponding buffers
Write to buffer with power-down command
(selected by DB17 and DB18) and then load all
DACs simultaneously from their corresponding
buffers
Simultaneously update all channels of all
X
DAC8164 devices in the system with data
stored in each channels data buffer
X
Write to all devices and load all DACs with SR
data
X
Write to all devices and load all DACs with
power-down command in SR
28
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